Dual polycrystalline silicon layers may be formed adjacent one another in various different types of semiconductor devices, including, for example, certain types of non-volatile memory devices. As shown in FIG. 1, formation of dual polycrystalline silicon layers typically involves the deposition of a first polycrystalline silicon layer 110 on an underlying layer 105 and then optional processing (not shown) of layer 110 to form various device structures (e.g., gates, etc.). Layer 110 may then be cleaned in an attempt to remove oxides and impurities, followed by an optional anneal at a high temperature to attempt to further remove oxides on layer 110. A second polycrystalline silicon layer 115 may then be deposited over layer 110. The cleaning and annealing processes, however, may not remove all oxides and impurities at the surface of layer 110, and residual oxide clusters 120 may be present on the surface of layer 110 prior to deposition of layer 115, thus, causing an imperfect interface 130 between polycrystalline silicon layers 110 and 115.
In the case wherein layer 110 is processed to produce a gate structure prior to formation of the second polycrystalline silicon layer, dopants for the gate are typically implanted into the top of the gate (i.e., into the upper surface of layer 110). In some circumstances, the dopants may cluster 125 at the surface of layer 110, thus, creating an undesirable depletion region at the interface 130 between layers 110 and 115.